1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, in particular, to integrated circuits including transistors having a stressed channel region.
2. Description of the Related Art
Integrated circuits include a large number of circuit elements, which include, in particular, field effect transistors. In a field effect transistor, a gate electrode is provided. The gate electrode may be separated from a channel region by a gate insulation layer providing electrical insulation between the gate electrode and the channel region. Adjacent the channel region, a source region and a drain region are provided.
The channel region, the source region and the drain region are formed of a semiconductor material, wherein the doping of the channel region is different from the doping of the source region and the drain region. Depending on an electric voltage applied to the gate electrode, the field effect transistor can be switched between an ON-state and an OFF-state, wherein an electric conductivity of the channel region in the ON-state is greater than an electric conductivity of the channel region in the OFF-state.
For improving the current through the channel region of a field effect transistor in the ON-state, an elastic stress can be provided in the channel region. A tensile stress can increase the mobility of electrons in a semiconductor material such as silicon. Providing a tensile stress in the channel region of an N-channel transistor can thus help improve the conductivity of the channel region, so that a greater current through the channel region in the ON-state of the transistor may be obtained. A compressive stress in a semiconductor material such as silicon can improve the mobility of holes, so that providing a compressive stress in the channel region of a P-channel transistor can help obtain a greater current through the channel region of the P-channel transistor in the ON-state of the transistor.
For providing an elastic stress in the channel regions of the transistors, the channel regions may be provided with a plurality of layers of different semiconductor materials. For example, a layer of silicon/germanium and a layer of silicon may be formed on a substrate base of silicon, for example on a silicon wafer. The layer of silicon/germanium is formed on the silicon substrate base, and the layer of silicon is formed on the layer of silicon/germanium. Silicon/germanium has a greater lattice constant than silicon. Due to the differences of the crystal lattice constants of the materials provided on top of each other, an elastic stress may be created.
As detailed above, for improving the performance of P-channel transistors and N-channel transistors, different types of stress may be required in the channel regions of the P-channel transistors and the N-channel transistors. If the above-mentioned technique for creating stress in the channel regions of transistors is employed, creating different stress in the channel regions of P-channel transistors and N-channel regions may be a problem, since, typically, a global stress in the silicon/germanium layer and/or in the silicon layer, for example, a biaxial stress in the top silicon layer is obtained. Hence, while the elastic stress created by the layers of silicon/germanium and silicon on the silicon substrate base may be beneficial for one type of transistor, it may be less than optimal for the other type of transistor.
The present disclosure provides devices and methods that address the above-mentioned problems.